An alternative approach to determining average distance in a class of scale-free modular networks

Various real-life networks of current interest are simultaneously scale-free and modular. Here we study analytically the average distance in a class of deterministically growing scale-free modular networks. By virtue of the recursive relations derived from the self-similar structure of the networks, we compute rigorously this important quantity, obtaining an explicit closed-form solution, which recovers the previous result and is corroborated by extensive numerical calculations. The obtained exact expression shows that the average distance scales logarithmically with the number of nodes in the networks, indicating an existence of small-world behavior. We present that this small-world phenomenon comes from the peculiar architecture of the network family.Comment: Submitted for publicactio

Intrinsic anomalous Hall effect across the magnetic phase transition of a spin-orbit-coupled Bose-Einstein condensate

We study theoretically the zero temperature intrinsic anomalous Hall effect in an experimentally realized 2D spin-orbit coupled Bose gas. For anisotropic atomic interactions and as the spin-orbit coupling strength increases, the system undergoes a ground state phase transition from states exhibiting a total in-plane magnetization to those with a perpendicular magnetization along the $z$ direction. We show that finite frequency, or ac, Hall responses exist in both phases in the absence of an artificial magnetic field, as a result of finite inter-band transitions. However, the characteristics of the anomalous Hall responses are drastically different in these two phases because of the different symmetries preserved by the corresponding ground states. In particular, we find a finite dc Hall conductivity in one phase but not the other. The underlying physical reasons for this are analyzed further by exploring relations of the dc Hall conductivity to the system's chirality and Berry curvatures of the Bloch bands. Finally, we discuss an experimental method of probing the anomalous Hall effect in trapped systems.Comment: 13 pages, 11 figure

A study of arithmetic circuits and the effect of utilising Reed-Muller techniques

Reed-Muller algebraic techniques, as an alternative means in logic design, became more attractive recently, because of their compact representations of logic functions and yielding of easily testable circuits. It is claimed by some researchers that Reed-Muller algebraic techniques are particularly suitable for arithmetic circuits. In fact, no practical application in this field can be found in the open literature.This project investigates existing Reed-Muller algebraic techniques and explores their application in arithmetic circuits. The work described in this thesis is concerned with practical applications in arithmetic circuits, especially for minimizing logic circuits at the transistor level. These results are compared with those obtained using the conventional Boolean algebraic techniques. This work is also related to wider fields, from logic level design to layout level design in CMOS circuits, the current leading technology in VLSI. The emphasis is put on circuit level (transistor level) design. The results show that, although Boolean logic is believed to be a more general tool in logic design, it is not the best tool in all situations. Reed-Muller logic can generate good results which can't be easily obtained by using Boolean logic.F or testing purposes, a gate fault model is often used in the conventional implementation of Reed-Muller logic, which leads to Reed-Muller logic being restricted to using a small gate set. This usually leads to generating more complex circuits. When a cell fault model, which is more suitable for regular and iterative circuits, such as arithmetic circuits, is used instead of the gate fault model in Reed-Muller logic, a wider gate set can be employed to realize Reed-Muller functions. As a result, many circuits designed using Reed-Muller logic can be comparable to that designed using Boolean logic. This conclusion is demonstrated by testing many randomly generated functions.The main aim of this project is to develop arithmetic circuits for practical application. A number of practical arithmetic circuits are reported. The first one is a carry chain adder. Utilising the CMOS circuit characteristics, a simple and high speed carry chain is constructed to perform the carry operation. The proposed carry chain adder can be reconstructed to form a fast carry skip adder, and it is also found to be a good application for residue number adders. An algorithm for an on-line adder and its implementation are also developed. Another circuit is a parallel multiplier based on 5:3 counter. The simulations show that the proposed circuits are better than many previous designs, in terms of the number of transistors and speed. In addition, a 4:2 compressor for a carry free adder is investigated. It is shown that the two main schemes to construct the 4:2 compressor have a unified structure. A variant of the Baugh and Wooley algorithm is also studied and generalized in this work

Synchronization in starlike networks of phase oscillators

We fully describe the mechanisms underlying synchronization in starlike networks of phase oscillators. In particular, the routes to synchronization and the critical points for the associated phase transitions are determined analytically. In contrast to the classical Kuramoto theory, we unveil that relaxation rates to each equilibrium state indeed exist and remain invariant under three levels of descriptions corresponding to different geometric implications. The special symmetry in the coupling determines a quasi-Hamiltonian property, which is further unveiled on the basis of singular perturbation theory. Since starlike coupling configurations constitute the building blocks of technological and biological real world networks, our paper paves the way towards the understanding of the functioning of such real world systems in many practical situations